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preliminary specifications cmos lsi le25fw406m le25fw406 t 4m-bit (512k x 8) serial flash memory *this product incorporate technology licensed from silicon storage technology, inc. this preliminary specification is subjected to change without notice. sanyo electric co., ltd. semiconductor company 1-1, 1 chome, sakata, oizumi-machi, ora-gun, gunma, 370-0596 japan revision 2.2 ? jun. 26, 2004 1/18 outline le25fw406 is 512k x 8-bit serial flash memory by 3.0v single power supply operation, and support serial peripheral interface (s.p.i.). there are two kinds of erase functions, chip erase, sector (64k bytes) erase. moreover, page program can program the arbitrary data to 1 byte from 256 bytes. program time is 30us/byte(typ.), 1.5ms/ 256bytes(typ.), and high speed. it is best suited for application that requires re-programmable nonvolatile mass storage of program or data memory. feature z read / write operation by the 3.0v single power supply are possible: power supply voltage range 2.7-3.6v z clock frequency: 30 mhz / 50mhz (planning) z temperature range: 0 ~ +70 c / -40 ~ +85 c (planning) z serial interface: spi mode0 and mode3 correspondence z sector size: 64 k bytes / sector z sector erase, chip erase function z page program (256 bytes/page) z block protection z a high reliability read / write endurance cycles: 100,000 times sector erase time: 25ms (typ.) 0.5s (max.) chip erase time: 250ms (typ.) 5s (max.) page program time: 40 us/byte (typ.) 1.5ms/256 bytes (typ.) 2.5 ms/256 bytes (max.) z status function: ready / busy information, erase time excess information, protection information z data retention: 10 years z package available: le25fw406m sop8 LE25FW406T msop8 figure 1: pin assignment
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 2 figure 2: block diagram table 1: pin description symbol pin description function sck serial clock to control the timing of serial data input and output. to latch input data and addresses synchronously at the rising edge of sck, and read out output data synchronously at the falling edge. si serial data input to input data or addresses serially from msb to lsb (least significant bit). so serial data output to output data serially from msb to lsb. cs# chip select to activate the device when this pin is low. to deselect and put the device to standby mode when this pin is high. wp# write-protect to write-protect the block protect bits (bp0, bp1, bp2) and the status register write protect bit (srwp) of the status register in co-operation with the status register write protect bit (srwp). hold# hold to pause any serial communications with the device without deselecting the device. vdd power supply to provide from 2.7v to 3.6v supply vss ground 4m bit flash eeprom cell array y-decoder i/o buffers & data latches cs# sck si hold# wp# so x- decoder address buffers & latches serial interface control logic
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 3 table 2: commands summary command the 1st bus cycle (op- code) the 2nd bus cycle the 3rd bus cycle the 4th bus cycle the 5th bus cycle the 6th bus cycle the n-th bus cycle 03h a23-a16 a15-a8 a7-a0 read 0bh a23-a16 a15-a8 a7-a0 x sector erase d8h a23-a16 x x chip erase c7h page program 02h a23-a16 a15-a8 a7-a0 pd *1 pd *1 pd *1 write enable 06h write disable 04h power down b9h status register read 05h status register write 01h data software reset ffh read id release from power down abh x x a7-a0 *2 definition of table 2: x = don't care, h = hexadecimal notation, a23~a19 are don't care for all commands *1. pd: page program data. the arbitrary numbers of data of 1~256 bytes of byte unit for input. *2. read id a7~a1 are don't care. a read cycle from address a0=?0? outputs the manufacture code (sanyo: 62h). a read cycle at a ddress a0=?1? outputs the device code (07h). table 3: status register bit name logic function default at power up 0 ready state bit0 rdy# 1 a erase / program state 0 0 write prohibition state bit1 wen 1 write possible state 0 0 bit2 bp0 1 non-volatile information 0 bit3 bp1 1 non-volatile information 0 bit4 bp2 1 the block protect information reference status registers non-volatile information 0 erase / program normal operation / normal end bit5 error 1 erase / program time excess state 0 bit6 reserve bit 0 0 status register write enable state bit7 srwp 1 status register write disable state non-volatile information device operation
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 4 le25fw406 is the product that supports the serial interface, and has the electric on-chip erase by the 3.0v single power supply and the function of standard eprom for industrial. the interface and control are made easily by building a command register in a chip. reading, erasing, programming, and a function required in addition to them are performed through a command register. the address and data of command are latched for program and erase operation. figure3 and figure4 indicate the timing waveform of serial input and output. while cs# is low, the device will be chosen and the input of a command, an address, etc. can be attained serially. those inputs are performed from bit7 (msb) synchronizing with the rising edge of sck. at this time, an output terminal (so) is in a high impedance state. it is that an output terminal (so) will be in a low impedance state at the time of a read, a status register read, and silicone id, and data is outputted from bit7 (msb) synchronizing with falling edge of a clock. le25fw406 support the both sides of serial interface spi mode0 and spi mode3. in case cs# falling edge, if sck is in a logic low level state and it is in spi mode0, and if a high level state, spi mode3 will be chosen automatically. command definition table2 contains a command list and a brief summary of the commands. the following is a detailed description of the options initiated by each command. 1. read figure5 shows timing waveform of a read operation. there are two kinds of read commands, 4th bus read and 5th bus read. the 4th bus read is constituted from the 1st bus cycle to the 4th bus cycle. if 24-bit address is inputted after op-code (03h), the data of the specified address will be outputted synchronizing with sck. a data is outputted from the falling edge clock of the 4th bus cycle bit0. 5th bus read is constituted from the 1st bus cycle by the 5th bus cycle, which consists of 24 bits address and 8-bit dummy bit after op-code (0bh). the data is outputted from the falling edge clock of the 5th bus cycle bit0. the only one difference between these two commands is with or without a dummy bit input (5th bus cycle). while having inputted sck, the increment of the address is automatically carried out inside a device, and data is outputted in order until the top address (7ffffh) up to. if the data is outputted and the input of sck continues still more, it returns to the lowest address (00000h) and a data output is continued. by making cs# into a logic high level, a device is deselecting, and read cycle is ended. output terminal will be in a high impedance state. 2. status register the status register's contents are shown in table3. the status register can perform detection state of a device and setup of protection. 2-1. status register read the status register's contents can be read by status register read, moreover it can read also during the following operation. ? sectors erase ? chips erase ? page program ? status register write figure6 shows timing waveform of a status register read. status register command consists of only the 1st bus, if op- code (05h) dose writes in, synchronizing with falling edge of sck, the status register's contents will be outputted from srwp (bit7). if the data is outputted until rdy# (bit0), and also sck input continues still more, it returns to srwp and data output is continued. data is outputted from the falling edge clock of the 1st bus cycle bit0. status register read can be read always (also in case of inside of program cycle or erase cycle). 2-2. status register write by status register write, bp0, bp1, bp2 and srwp can be rewritten. bsy#, wen, error, and bit6 are read-only, bp0, bp1, bp2 and srwp are non-volatile. a timing waveform is shown in figure7 and a flow chart is shown in figure18. status register write command consists of the 1st bus cycle and the 2nd bus cycle, and internal write operation starts with the rising edge of cs# after inputting data after op-code (01h). erase and program are automatically performed inside the device and a status register write rewrites bp0, bp1, bp2 and srwp non- volatilized data. the write-in data to read-only bits (rdy#, wen, error, bit 6) are don't care. the end of a status register write is detectable with rdy# of a status register read. the number of times of rewriting of a status register write is 10,000 times (min). in order to perform a status register write, it is necessary to change wen of a status register into "1" state for wp# pin. rdy#(bit0) the end of a write (program, erase, status register write) is detectable with rdy#. if device is in a busy state rdy# is in "1", and the write will be ended in "0" states.
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 5 wen (bit1) it is detectable whether a write is possible with wen. if wen is in "0" state, even if it inputs a write command, device will not perform write operation. if wen is in "1" state, write is possible to the area by which block protection is not carried out. wen is controllable with a write enable command and a write disable command. wen will be in "1" state with a write enable command (06h), and will be in "0" states with a write disable command (04h). moreover, in the following state, automatically, wen will be in "0" states and an unprepared write will be prevented. ? at the time of a power-up ? after sector erase, or chip erase is completed ? after a page program is completed ? after a status register write is completed bp0, bp1, bp2 (bit 2,3,4) block protection bp0, bp1 and bp2 can set up the memory address area to be protected. refer to table 4 for setting conditions. table 4: protection level setting conditions status register bit protection level bp2 bp1 bp0 protection area 0 (all area unprotect) 000 nothing 1 (1/8 protection) 001 70000h- 7ffffh 2 (1/4 protection) 010 60000h- 7ffffh 3 (1/2 protection) 011 40000h- 7ffffh 4 (all area protection) 100 00000h- 7ffffh 4 (all area protection) 101 00000h- 7ffffh 4 (all area protection) 110 00000h- 7ffffh 4 (all area protection) 111 00000h- 7ffffh * a chip erase is possible only when a protection level is 0. error (bit5) erase / program time excess flag error will be in "1" state, if an erase / program exceeds regulation marginal time. the regulation marginal time of page program is 10ms (typ.), sector erase is 2s (typ.), and chip erase is 10s (typ.). if an erase / program exceeds regulation marginal time, a device will be locked and an erase / program will not end it automatically (it continues being in a busy state). in order to make it end, it is necessary to perform software reset. srwp (bit7) status register write protection srwp protects status register. when "1" state and wp# pin are logic low levels, as for a status register write command, they are disregarded, and as for bp0, bp1 and bp2 of a status register, and srwp is protected. when wp# pin is a logic high level, a status register is not protected irrespective of the state of srwp. srwp setting conditions are shown in table 5. table 5: srwp setting conditions wp# pin srwp status register protection state 0 unprotect 0 1protection 0 unprotect 1 1 unprotect bit6 are reserve bit. 3. write enable write enable sets a status register wen to "1" state. in order to perform the following operation, it is necessary to execute a write enable command first. ? sector erase ? chip erase ? page program ? status register write figure8 shows timing waveform. a write enable command consists of only the 1st bus cycle. op-code is 06h. 4. write disable write disable sets a status register wen to "0" states, and forbids an unprepared write. figure9 shows timing waveform. write enable command consists of only the 1st bus cycle. op-code is 04h. to release from a write disable state (wen "0"), it should be performed the write enable command (06h). 5. power down power down states carry out the prohibition state of all the commands except read id and power down release command. figure10 shows timing waveform. power down command consists of only the 1st bus cycle. op-code is b9h. for release from power down mode, power down release command performs to abort. figure11 shows release from power down timing waveform. and figure15 shows read id timing waveform. 6. sector erase sector erase changes the memory cell data of arbitrary sectors into "1" state. a sector consists of 64 k bytes. figure12 shows timing waveform and a flow chart is shown in figure19 sector erase command is constituted from the 1st bus cycle to the 4th bus cycle, 24-bit address after op-code (d8h). as for the address, a18 - a16 are effective, and the rest is don't care. erase operation begins from the rising edge of cs# after a command input end, and it ends automatically by control of an internal timer. moreover, the end of an erase is detectable by using status register. however, when it becomes an excess of an erase time (a status register error is "1" state), sector erase mode is not ended automatically. in order to make it end, it is necessary to perform software reset input.
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 6 7. chip erase chip erase changes the memory cell data of all sectors into "1" state. figure13 shows timing waveform and a flow chart is shown in figure20. chip erase command consists of only the 1st bus cycle. op- code is c7h. after a command input end, by the rising edge of cs#, erase operation starts and it ends automatically by control of an internal timer. moreover, the end of an erase is detectable by using status register. however, when it becomes an excess of an erase time (a status register error is "1" state), chip erase mode is not ended automatically. in order to make it end, it is necessary to perform software reset input. 8. page program page program can program the arbitrary numbers of bytes of 1 to 256 bytes into the sector erased in advance. figure14 shows timing waveform and a flow chart is shown in figure20. 24-bit address is inputted after op-code (02h). as for an address a18-a0 are effective. then, loading is possible for program data during cs# is low. when the data loaded exceeds 256 bytes, 256 bytes loaded at the end are programmed. it is necessary to load program data per byte, and when it programs by loading the data below a byte unit, a normal page program is not performed. for page program time, it is dependent on the amount of data, and if data is 32 bytes or under, program time is 30 us/byte (typ.). in case of more than 32 bytes, program time is 1.5ms (typ.). however, when it becomes an excess of an program time (a status register error is "1" state), page program mode is not ended automatically. in order to make it end, it is necessary to perform software reset input. 9. read id read id can read the information on a manufacturer code and a device code. figure15 shows timing waveform and the silicone id code table is shown in table 6. read id command is constituted from the 1st bus cycle to the 4th bus cycle. an address of 16bit dummy bit and 8 bits is inputted after op-code (abh), it can read silicone id. in address a0 ="0", a manufacturer code is read for 62h by the 5th bus cycle, and device code is read for 07h by the 6th bus cycle. when sck input still continues more, manufacturer code and a device code are outputted by turns in bus cycle. in address a0 ="1", read-out begins from 07h of a device code in the 5th bus cycle. read id cannot perform under write execution. table 6: the silicone id code table address a0 output code manufacturer code 0 62h device code 1 07h a data output is outputted from the falling edge clock of the 4th bus cycle bit0, it is making cs# into a logic high level, and a read id is ended. 10. software reset software reset can release from an erase or program time excess state. the timing waveform of software reset is shown in figure16. software reset command consists of only the 1st bus cycle. op-code is ffh. after a command input end, if cs# is rising edge, it will be reset. it resets error of status register information. 11. hold function hold# pin is used in order to pause serial communication (hold state). the timing waveform is shown in figure17. if hold# starts to falling edge in the timing sck on a logic low level, device will be in a hold state. and if hold# starts to rising edge, device will release from hold state in same timing. changes of hold# are forbidden when clk is high level. if it is effective when cs# is a logic low level, and when cs# is rising edged, it will release from a hold state and serial communication will be reset. in a hold state, so is hi-z, si and sck is don't care. 12. hardware data protection in order to prevent the unprepared writing at power-up, le25fw406 have the power-on reset function inside. 13. decoupling capacitor ceramic capacitors (0.1uf) must be added between vdd and vss to each device to assure stable flash memory operation.
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 7 absolute maximum stress ratings storage temperature ................................................... -55 c ~ 150 c supply voltage .............................................................. -0.5 v ~ 4.6 v d.c . voltage on any pin to grand potential ..................-0.5 v ~ vdd + 0.5 v o perating range ambient temperature .................................................... 0 c ~ 70 c / -40 c ~ 85 c (planning) vdd ............................................................................... 2.7 v ~ 3.6 v dc operating characteristics limit symbol parameter min. max. unit test conditions 4ma cs# = vil, hold# = wp# = vih, so = open, si = vil/vih, clock frequency = 25 mhz, vdd = vdd max 6ma cs# = vil, hold# = wp# = vih, so = open, si = vil/vih, clock frequency = 30 mhz, vdd = vdd max iccr power supply current (read) 8ma cs# = vil, hold# = wp# = vih, so = open, si = vil/vih, clock frequency = 50 mhz, vdd = vdd max iccw power supply current (write) 15 ma vdd = vdd max. isb1 ttl standby current 3 ma cs# = hold# = wp# = vih and so = open, si = vih/vil, vdd = vdd max isb2 cmos standby current 5 a cs# = hold# = wp# = vdd - 0.3v and so = open, si = vih/vil, vdd = vdd max ili input leakage current 2 a vin = vss - vdd, and vdd = vdd max ilo output leakage current 2 a vin = vss - vdd, and vdd = vdd max vil input low voltage - 0.3 0.3vdd v vdd = vdd max. vih input high voltage 0.7vdd vdd + 0.3 v vdd = vdd min. 0.2 iol = 100 ua, vdd = vdd min. vol output low voltage 0.4 v iol = 1.6 ma, vdd = vdd min. voh output high voltage vdd - 0.2 v ioh = - 100 ua, vdd = vdd min. power-up timing symbol parameter min. units tpu_read power-up to read operation 10 ms tpu_write power-up to write operation 10 ms capacitance (ta = 25 c, f = 1 mhz) symbol description max. unit test condition cdq dq pin capacitance 12 pf vdq = 0v cin input capacitance 6 pf vin = 0v note: these parameters are periodically sampled and are not 100% tested.
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 8 ac characteristic (fclk=30mhz operation) limit symbol parameter min. typ. max. unit fclk clock frequency 30 mhz trf input rising, falling time 20 ns tcss cs# setup time 10 ns tcsh cs# hold time 10 ns tcph cs# standby pulse width 25 ns tchz cs# to high-z output 15 ns tds data setup time 5 ns tdh data hold time 5 ns tcls sck setup time 10 ns tclh sck hold time 10 ns tclhi sck high pulse width 16 ns tcllo sck low pulse width 16 ns tclz sck to low-z output 0 ns tv sck to output valid 815ns tho output data hold time 0 ns tse sector erase cycle time 0.025 0.5 s tche chip erase cycle time 0.25 5 s page program cycle time per byte (1 byte - 32 bytes) 40 50 us tpp page program cycle time (33 bytes - 256 bytes) 1.5 2.5 ms tsrw write status register cycle time 5 15 ms twps wp# setup time 20 ns twph wp# hold time 20 ns trb reset recovery time 100 ns tprb power down recovery time 25 ns ths hold# setup time 7 ns thh hold# hold time 3 ns thhz hold# low to high-z output 9ns thlz hold# high to low-z output 9ns ac test conditions input pulse level ............................................... 0 v, 3.0 v input rise/fall time ...........................................5 ns input/output timing level ..................................1/2 vdd output load ??............................................... 30 pf
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 9 ac characteristic (fclk=50mhz operation) limit symbol parameter min. typ. max. unit fclk clock frequency 50 mhz trf input rising, falling time 20 ns tcss cs# setup time 8 ns tcsh cs# hold time 8 ns tcph cs# standby pulse width 25 ns tchz cs# to high-z output 8ns tds data setup time 2 ns tdh data hold time 5 ns tcls sck setup time 5 ns tclh sck hold time 5 ns tclhi sck high pulse width 9ns tcllo sck low pulse width 9 ns tclz sck to low-z output 0 ns tv sck to output valid 9ns tho output data hold time 0 ns tse sector erase cycle time 0.025 0.5 s tche chip erase cycle time 0.25 5 s page program cycle time per byte (1 byte - 32 bytes) 40 50 us tpp page program cycle time (33 bytes - 256 bytes) 1.5 2.5 ms tsrw write status register cycle time 5 15 ms twps wp# setup time 20 ns twph wp# hold time 20 ns trb reset recovery time 100 ns tprb power down recovery time 25 ns ths hold# setup time 7 ns thh hold# hold time 3 ns thhz hold# low to high-z output 9ns thlz hold# high to low-z output 9ns ac test conditions input pulse level ............................................... 0 v, 3.0 v input rise/fall time ...........................................5 ns input/output timing level ..................................1/2 vdd output load ??............................................... 30 pf
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 10 timing waveforms figure 3: serial input timing diagram (spi mode 0) high impedance t dh t cph t ds t csh t css cs# data valid so si sck high impedance t clh t cls t clhi t cllo (spi mode 3) high impedance t dh t cph t ds t csh t css cs# so si sck high impedance data valid t clh t cls t clhi t cllo
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 11 figure 4: serial output timing diagram (spi mode 0) t ho t chz t clz si t v cs# so sck data valid (spi mode 3) t ho t chz t clz si t v cs# so sck data valid
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 12 figure 5: read cycle timing diagram 4th bus read n+2 n+1 n cs high impedance data data data sck so si 03h add. add. add. 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 47 8clk mode0 mode3 32 40 5th bus read n+2 n+1 n cs# high impedance data data data sck so si 0bh add. add. add. x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 48 55 mode3 mode0 8clk figure 6: read status register diagram cs# sck si so msb msb msb 05h data data high impedance 8 3 2 1 0 7 6 5 4 15 23 mode3 mode0 8clk 16 data
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 13 figure 7: write status register diagram t srw self-timed write cycle sck si high impedance so cs# data 01h 15 0 1 2 3 4 5 6 7 8 mode3 mode0 8clk w p# t wph t wps figure 8: write enable diagram figure 9: write disable diagram sck si high impedance so cs# 06h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs# 04h 0 1 2 3 4 5 6 7 mode3 mode0 8clk figure 10: power down diagram figure 11: escape from power down diagram sck si high impedance so cs# b9h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs# abh 0 1 2 3 4 5 6 7 mode3 mode0 8clk tprb
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 14 figure 12: sector erase diagram sck si high impedance so cs# t se self-timed erase cycle add. d8h add. x 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk figure 13: chip erase diagram sck si high impedance so cs# t che self-timed erase cycle c7h 0 1 2 3 4 5 6 7 mode3 mode0 8clk
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 15 figure 14: page program diagram t pp self-timed program cycle sck si high impedance so cs# pd add. add. 02h add. pd 15 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 mode3 mode0 8clk pd 2079 figure 15: read id diagram n n+1 n cs# high impedance siid siid siid sck so si abh add. x x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 39 47 8clk mode0 mode3 32 40 figure 16: software reset timing diagram cs# sck si so ffh high impedance t rb 0 1 2 3 4 5 6 7 mode3 mode0 8clk
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 16 figure 17: hold command diagram cs# hold# sck so active hold active th h ths thlz thhz high impedance th h ths figure 18: status register write flow chart status register write start 05h status register read command is set status register write command is set it program-starts with the standup edge of cs#. status register write yes bit 0= "1"? 06h write 01h no it becomes a write disable automatically after status register write end. data
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 17 figure 19: erase flow chart start 05h status registers read command is set. sector erase command is set address 1 dummy it erase-starts with the standup edge of cs#. erase end erase time excess yes bit 5 = "0"? bit 0 = "1"? yes no sector erase dummy 06h write enable d8h no it becomes a write disable automaticall y after an erase end. start 05h status register read command is set. chip erase command is set. it erase-starts with the standup edge of cs#. erase end erase time excess yes bit 5 = "0"? bit 0 = "1"? yes no chips erase 06h write enable c7h no it becomes a write disable automatically after an erase end. it does not end automatically from an erase state. it resets, in order to make it end. it does not end automatically from an erase state. it resets, in order to make it end.
le25fw406m / LE25FW406T 3.0v only 4 m-bit serial flash memory preliminary specifications sanyo electric co., ltd. no. 18 figure 20: program flow chart page program start 05h status register read command is set. page program command is set address 1 address 2 it program-starts with the standup edge of cs#. program end yes bit 0= "1"? address 3 06h write enable 02h no it becomes a write disable automaticall y after p ro g ram end. data 0 data n 1. no products described or contained herein are intended for use in surgical implants, life-support systems aerospace equipmen t, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, then failure of which may directly o r indirectly cause injury, death or property loss. 2. anyone purchasing any products described or contained herein for an above-mentioned use shall: a) accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost an d expenses associated with such use: b) not impose any responsibility for any fault or negligence, which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributor or any of their officers and employees jointly or sever ally. 3. information (including circuit diagrams and circuit parameter) herein in for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringement of intellectual property rights or other rights of third parties program time excess yes bit 5 = "0"? no it does not end automatically from an program state. it resets, in order to make it end.

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